EN0-001 ARM Accredited Engineer Questions and Answers

Fetch, Decode, Execute

Decode, Fetch, Execute

Execute, Fetch, Decode

Fetch, Execute, Execute

Cache control operations

Address translation operations

Debug control and status information

Architecture feature ID registers

ARM926EJ-S

Cortex-M0

Cortex-M3

Cortex-A8

If a TLB miss occurs

On every process switch

If the TLB reports a fault

When a page table entry is changed

Any processor in the cluster

Only the processor raising the software-generated interrupt

Only processors outside the cluster

Any processor except the one raising the software-generated interrupt

bits [5:0]

bits [7:2]

bits [15:10]

bits [31:26]

SWP and SWPB

DSB and ISB

LDREX and STREX

DMB

Core register contents

CP15 (system) register settings

Debug state

Cache contents

FIQ exceptions must not be taken

The instruction cache must be enabled

Global variables must be initialized to zero

The Reset Vector must reside in non-volatile memory

This transition is not possible

Execution of an SMC instruction

Execution of an SMC instruction followed by an SVC instruction

Execution of an SVC instruction followed by an SMC instruction

Disabling inlining.

Never passing more than four parameters in function calls.

Declaring automatic variables as "packed".

Configuring the compiler to optimize for space.

Interrupt from a private peripheral to a processor

Interrupt from a processor to a private peripheral

Interrupt from a shared peripheral to a processor

Interrupt from a processor to a shared peripheral

Interrupt from a private peripheral to a shared peripheral

Interrupt from a shared peripheral to a private peripheral

Coherency management between all L1 data caches

Broadcast of some inner-shared cache and TLB maintenance operations

Broadcast of some outer-shared cache and TLB maintenance operations

Coherency management between all L1 instruction caches

Coherency management between all external caches

Encrypting sensitive data on a network

Preventing interrupts from being received by a CPU

Preventing unauthorized access to an ARM powered device

Protecting a critical section or data structure from concurrent access

It allows a complete trace of real-time program execution to be captured

It reduces the number of pins required to connect the debugger to the processor

It allows examination of the system state before and after execution of a statement

It requires only one change to the program source code

VA == PA; No address translations; instructions and data are not cached

VA! = PA; No address translations; instructions may be cached but not data

VA == PA; Address translations take place; data may be cached but not instructions

VA == PA; No address translations; instructions may be cached but not data

L1 Caches and branch prediction are disabled

The Embedded Trace Macrocell (ETM) is disabled

The Memory Management Unit (MMU) is enabled

The Snoop Control Unit (SCU) is disabled

Top address of RAM (0x18000)

Top address of flash (0x8000)

Bottom address of RAM (0x10000)

Bottom address of flash (0x0000)

The processor is context switching between multiple processes

Performance is limited by the speed of external memory

The processor is taking too long to execute branch instructions

The system is raising interrupts too fast for the processor to handle them

Shareable Memory

Snoop Control Unit

Private Memory Region

Level 2 Cache Controller

0x00000000

0xFFFFFFFF

0x11111111

0xAAAAAAAA

Supervisor Call

FIQ

Undefined Instruction

Parity

Put the processor(s) into debug state.

Force the processor to execute a BKPT instruction

Hold the processor in a Reset condition

Re-initialize the memory contents.

R2 = 0xBB

R2 = 0xCB

R2 = 0xAA

R2 = 0xCC

Allow an external interrupt to interrupt an SVC handler

Reduce response time for higher priority interrupts

Allow an interrupt handler to be relocated in memory

Avoid the need for an interrupt handler to use a stack.

Protect memory.

Improve performance.

Implement virtual memory,

Ensure correct ordering of memory operations.

Additional quadword registers

Support for double precision floating-point arithmetic

Fused Multiply-Accumulate (Fused MAC) instructions

Support for polynomials

Storage can be easily replaced, for example to increase capacity.

It is quicker to access, providing far greater bandwidth for read operations.

It has a longer life, indicated by being rated for a higher number of write cycles.

It takes up less physical space in a device, and does not require any space on the printed circuit board.